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TDA7449 tone control digitally controlled audio processor input multiplexer - 2 stereo inputs - selectable input gain for optimal adaptation to different sources one stereo output treble, and bass control in 2.0db steps volume control in 1.0db steps two speaker attenuators: - two independent speaker control in 1.0db steps for balance facility - independent mute function all function are programmable via serial bus description the TDA7449 is a volume tone (bass and treble) balance (left/right) processor for quality audio applications in tv systems. selectable input gain is provided. control of all the functions is accomplished by serial bus. the ac signal setting is obtained by resistor net- works and switches combined with operational amplifiers. thanks to the used bipolar/cmos technology, low distortion, low noise and dc stepping are obtained. april 1999 ? 0/30db 2db step muxoutl volume volume treble treble treble(l) bass bass muxoutr treble(r) spkr att left lout scl sda dig_gnd rout d98au847a i 2 cbus decoder + latches 100k 100k g l-in1 l-in2 100k 100k r-in1 r-in2 g input multiplexer + gain bout(l) spkr att right bin(r) bout(r) supply cref agnd v s bin(l) 5 8 9 7 6 19 20 18 4 2 3 11 17 12 13 1 10 16 15 14 r b r b v ref block diagram ordering number: TDA7449 dip20 1/17
absolute maximum ratings symbol parameter value unit v s operating supply voltage 10.5 v t amb operating ambient temperature -10 to 85 c t stg storage temperature range -55 to 150 c thermal data symbol parameter value unit r th j-pin thermal resistance junction-pins 150 c/w cref v s pgnd rout lout r_in1 r_in2 l_in1 l_in2 1 3 2 4 5 6 7 8 9 bin(r) bout(r) bout(l) treble(l) bin(l) treble(r) dig_gnd scl sda 20 19 18 17 16 14 15 13 12 d98au848 muxout(l) 10 muxout(r) 11 pin connection quick reference data symbol parameter min. typ. max. unit v s supply voltage 6 9 10.2 v v cl max. input signal handling 2 vrms thd total harmonic distortion v = 1vrms f = 1khz 0.01 0.1 % s/n signal to noise ratio v out = 1vrms (mode = off) 106 db s c channel separation f = 1khz 90 db input gain in (2db step) 0 30 db volume control (1db step) -47 0 db treble control (2db step) -14 +14 db bass control (2db step) -14 +14 db balance control 1db step -79 0 db mute attenuation 100 db TDA7449 2/17
electrical characteristics (refer to the test circuit t amb = 25c, v s = 9v, r l = 10k w , r g = 600 w , all controls flat (g = 0db), unless otherwise specified) symbol parameter test condition min. typ. max. unit supply v s supply voltage 6 9 10.2 v i s supply current 7 ma svr ripple rejection 60 90 db input stage r in input resistance 100 k w v cl clipping level thd = 0.3% 2 2.5 vrms s in input separation the selected input is grounded through a 2.2 m capacitor 80 100 db g inmin minimum input gain -1 0 1 db g inman maximum input gain 30 db g step step resolution 2 db volume control c range control range 45 47 49 db a vmax max. attenuation 45 47 49 db a step step resolution 0.5 1 1.5 db e a attenuation set error a v = 0 to -24db -1.0 0 1.0 db a v = -24 to -47db -1.5 0 1.5 db e t tracking error a v = 0 to -24db 0 1 db a v = -24 to -47db 0 2 db v dc dc step adjacent attenuation steps from 0db to a v max 0 0.5 3mv mv a mute mute attenuation 80 100 db bass control (1) gb control range max. boost/cut +12.0 +14.0 +16.0 db b step step resolution 1 2 3 db r b internal feedback resistance 18.75 25 31.25 k w treble control (1) gt control range max. boost/cut +13.0 +14.0 +15.0 db t step step resolution 1 2 3 db speaker attenuators c range control range 76 db s step step resolution 0.5 1 1.5 db e a attenuation set error a v = 0 to -20db -1.5 0 1.5 db a v = -20 to -56db -2 0 2 db v dc dc step adjacent attenuation steps 0 3 mv a mute mute attenuation 80 100 db note1: 1) the device is functionally good at vs = 5v. a step down, on vs, to 4v doest reset the device. 2) bass and treble response: the center frequency and the response quality can be chosen by the external circuitry. TDA7449 3/17
electrical characteristics (continued.) symbol parameter test condition min. typ. max. unit audio outputs v clip clipping level d = 0.3% 2.1 2.6 v rms r l output load resistance 2 k w r o output impedance 10 40 70 w v dc dc voltage level 3.8 v general e no output noise all gains = 0db; bw = 20hz to 20khz flat 515 m v e t total tracking error a v = 0 to -24db 0 1 db a v = -24 to -47db 0 2 db s/n signal to noise ratio all gains 0db; v o = 1v rms ; 106 db s c channel separation left/right 80 100 db d distortion a v = 0; v i = 1v rms ; 0.01 0.08 % bus input v il input low voltage 1 v v ih input high voltage 3 v i in input current v in = 0.4v -5 5 m a v o output voltage sda acknowledge i o = 1.6ma 0.4 0.8 v TDA7449 4/17
0/30db 2db step muxoutl volume volume treble treble treble(l) bass bass muxoutr treble(r) spkr att left lout scl sda dig_gnd rout d98au849a i 2 cbus decoder + latches 100k 100k g l-in1 l-in2 100k 100k r-in2 r-in1 g input multiplexer + gain bout(l) spkr att right bin(r) bout(r) supply cref agnd v s bin(l) 5 8 9 6 7 19 20 18 4 2 3 11 17 12 13 1 10 16 15 14 r b r b v ref c9 5.6nf 150nf 330nf r2 2k c10 5.6nf 150nf 330nf r1 c3 0.47 m f c4 0.47 m f c1 0.47 m f c2 0.47 m f c11 10 m f 1 2 3 4 5 rca j3 j4 con3 in2l in1l gnd gnd gnd in1l rca j2 j1 con in1r in2r gnd gnd in1r 1 2 3 4 1 2 3 4 moutr gnd moutl j5 j5 con4 gnd c5 c6 2k c8 c7 1 2 3 4 j6 con4 r3 30 jp1 jumper +9 v 1 2 3 4 j10 con4 j8 j9 out_ r out_l out_r out_l 1 2 +9v j7 con2 c13 100nf c12 22 m f +v8 gnd test circuit p.c.board TDA7449 5/17
application suggestions the first and the last stages are volume control blocks. the control range is 0 to -47db (mute) for the first one, 0 to -79db (mute) for the last one. both of them have 1db step resolution. the very high resolution allows the implementation of systems free from any noisy acoustical effect. the TDA7449 audioprocessor provides 2 bands tones control. bass, stages the bass cell has an internal resistor ri = 25k w typical. several filter types can be implemented, connect- ing external components to the bass in and out pins. the fig.1 refers to basic t type bandpass filter starting from the filter component values (r1 in- ternal and r2,c1,c2 external) the centre fre- quency fc, the gain av at max. boost and the fil- ter q factor are computed as follows: f c = 1 2 p ? `````````````` ri, r2, c1, c2 a v = r2 c2 + r2 c1 + ri c1 r2 c1 + r2 c2 q = ? ````````````` ` ri r2 + c1 c2 r2 c1 + r2 c2 viceversa, once fc, av, and ri internal value are fixed, the external components values will be: c1 = a v - 1 2 p r i q c2 = q 2 c1 ( a v - 1 ) q 2 r2 = a v - 1 - q 2 2 p c1 f c ( a v - 1 ) q treble stage the treble stage is a high pass filter whose time constant is fixed by an internal resistor (25k w typical) and an external capacitor connected be- tween treble pins and ground typical responses are reported in figg. 10 to 13. cref the suggested 10 m f reference capacitor (cref) value can be reduced to 4.7 m f if the application requires faster power on. ri internal c 2 out in c 1 r 2 d95au313 figure 1. figure 2: thd vs. frequency figure 3: thd vs. r load TDA7449 6/17
figure 4: channel separation vs. frequency figure 6: treble response figure 5: bass response r i = 25k w c1 = 150nf c2 = 330nf r2 = 2k w TDA7449 7/17
i 2 c bus interface data transmission from microprocessor to the TDA7449 and vice versa takes place through the 2 wires i 2 c bus interface, consisting of the two lines sda and scl (pull-up resistors to positive supply voltage must be connected). data validity as shown in fig. 3, the data on the sda line must be stable during the high period of the clock. the high and low state of the data line can only change when the clock signal on the scl line is low. start and stop conditions as shown in fig.4 a start condition is a high to low transition of the sda line while scl is high. the stop condition is a low to high tran- sition of the sda line while scl is high. byte format every byte transferred on the sda line must con- tain 8 bits. each byte must be followed by an ac- knowledge bit. the msb is transferred first. acknowledge the master ( m p) puts a resistive high level on the sda line during the acknowledge clock pulse (see fig. 5). the peripheral (audio processor) that ac- knowledges has to pull-down (low) the sda line during this clock pulse. the audio processor which has been addressed has to generate an acknowledge after the recep- tion of each byte, otherwise the sda line remains at the high level during the ninth clock pulse time. in this case the master transmitter can gen- erate the stop information in order to abort the transfer. transmission without acknowledge avoiding to detect the acknowledge of the audio processor, the m p can use a simpler transmission: simply it waits one clock without checking the slave acknowledging, and sends the new data. this approach of course is less protected from misworking. figure 3: data validity on the i 2 cbus figure 4: timing diagram of i 2 cbus f igure 5: acknowledge on the i 2 cbus TDA7449 8/17
software specification interface protocol the interface protocol comprises: a start condition (s) a chip address byte, containing the TDA7449 address a subaddress bytes a sequence of data (n byte + acknowledge) a stop condition (p) ack = acknowledge s = start p = stop a = address b = auto increment s 1 0 0 0 1 0 0 0 ack ack data ack p msb lsb msb lsb msb lsb chip address d96au420 x data subaddress data 1 to data n xxb examples no incremental bus the TDA7449 receives a start condition, the cor- rect chip address, a subaddress with the b = 0 (no incremental bus), n-data (all these data con- cern the subaddress selected), a stop condition. s 1 0 0 0 1 0 0 0 ack ack data ack p msb lsb msb lsb msb lsb chip address d96au421 xd3 subaddress data xx0 d2 d1 d0 incremental bus the TDA7449 receive a start conditions, the cor- rect chip address, a subaddress with the b = 1 (incremental bus): now it is in a loop condition with an autoincrease of the subaddress whereas subaddress from "xxx1000" to "xxx1111" of data are ignored. the data 1 concern the subaddress sent, and the data 2 concern the subaddress sent plus one in the loop etc, and at the end it receivers the stop condition. s 1 0 0 0 1 0 0 0 ack ack data ack p msb lsb msb lsb msb lsb chip address d96au422 xd3 subaddress data 1 to data n xx1 d2 d1 d0 TDA7449 9/17
power on reset condition input selection in2 input gain 28db volume mute bass 2db treble 2db speaker mute data bytes address = 88 hex (addr:open). function selection: first byte (subaddress) msb lsb subaddress d7 d6 d5 d4 d3 d2 d1 d0 x x x b 0 0 0 0 input select x x x b 0 0 0 1 input gain x x x b 0 0 1 0 volume x x x b 0 0 1 1 not allowed x x x b 0 1 0 0 bass x x x b 0 1 0 1 treble x x x b 0 1 1 0 speaker attenuate "r" x x x b 0 1 1 1 speaker attenuate "l" b = 1: incremental bus active b = 0: no incremental bus x = dont care input selection msb lsb input multiplexer d7 d6 d5 d4 d3 d2 d1 d0 x x x x x x 0 0 not allowed x x x x x x 0 1 not allowed xxxxxx1 0 in2 xxxxxx1 1 in1 TDA7449 10/17
data bytes (continued) input gain selection msb lsb input gain d7 d6 d5 d4 d3 d2 d1 d0 2db steps 0000 0db 0001 2db 0010 4db 0011 6db 0100 8db 0 1 0 1 10db 0 1 1 0 12db 0 1 1 1 14db 1 0 0 0 16db 1 0 0 1 18db 1 0 1 0 20db 1 0 1 1 22db 1 1 0 0 24db 1 1 0 1 26db 1 1 1 0 28db 1 1 1 1 30db gain = 0 to 30db volume selection msb lsb volume d7 d6 d5 d4 d3 d2 d1 d0 1db steps 0 0 0 0db 0 0 1 -1db 0 1 0 -2db 0 1 1 -3db 1 0 0 -4db 1 0 1 -5db 1 1 0 -6db 1 1 1 -7db 0000 0db 0001 -8db 0 0 1 0 -16db 0 0 1 1 -24db 0 1 0 0 -32db 0 1 0 1 -40db x 1 1 1 x x x mute volume = 0 to 47db/mute TDA7449 11/17
data bytes (continued) bass selection msb lsb bass d7 d6 d5 d4 d3 d2 d1 d0 2db steps 0 0 0 0 -14db 0 0 0 1 -12db 0 0 1 0 -10db 0011 -8db 0100 -6db 0101 -4db 0110 -2db 0111 0db 1111 0db 1110 2db 1101 4db 1100 6db 1011 8db 1 0 1 0 10db 1 0 0 1 12db 1 0 0 0 14db treble selection msb lsb treble d7 d6 d5 d4 d3 d2 d1 d0 2db steps 0 0 0 0 -14db 0 0 0 1 -12db 0 0 1 0 -10db 0011 -8db 0100 -6db 0101 -4db 0110 -2db 0111 0db 1111 0db 1110 2db 1101 4db 1100 6db 1011 8db 1 0 1 0 10db 1 0 0 1 12db 1 0 0 0 14db TDA7449 12/17
data bytes (continued) speaker attenuate selection msb lsb speaker attenuation d7 d6 d5 d4 d3 d2 d1 d0 1db 0 0 0 0db 0 0 1 -1db 0 1 0 -2db 0 1 1 -3db 1 0 0 -4db 1 0 1 -5db 1 1 0 -6db 1 1 1 -7db 0000 0db 0001 -8db 0 0 1 0 -16db 0 0 1 1 -24db 0 1 0 0 -32db 0 1 0 1 -40db 0 1 1 0 -48db 0 1 1 1 -56db 1 0 0 0 -64db 1 0 0 1 -72db 1 1 1 1 x x x mute speaker attenuation = 0 to -79db/mute 20k 20k cref v s d96au430 v s pin: 1 v s d96au434 20 m a rout 24 lout pins: 4, 5 TDA7449 13/17
v s d96au491 20 m a v s muxout gnd pins: 10,11 20 m a v s 100k v ref d96au425 in pins: 6,7,8,9 44k v s bout(r) d96au429 20 m a bout(l) pins: 13, 14 25k v s bin(r) d98au850 20 m a bin(l) pins: 12, 15 50k v s treble(r) d96au433 20 m a treble(l) pins: 16, 17 d96au424 20 m a scl pin: 19 TDA7449 14/17
d96au423 20 m a sda pin: 20 TDA7449 15/17
dip20 dim. mm inch min. typ. max. min. typ. max. a1 0.254 0.010 b 1.39 1.65 0.055 0.065 b 0.45 0.018 b1 0.25 0.010 d 25.4 1.000 e 8.5 0.335 e 2.54 0.100 e3 22.86 0.900 f 7.1 0.280 i 3.93 0.155 l 3.3 0.130 z 1.34 0.053 outline and mechanical data TDA7449 16/17
information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsib ility for the cons equences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specification mentioned in this pu blication are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectron ics products are not authorized for use as critical components in life support devices or systems without express written approval of stmicr oelectronics. the st logo is a registered trademark of stmicroelectronics ? 1999 stmicroelectronics C printed in italy C all rights reserved stmicroelectronics group of companies australia - brazil - canada - china - france - germany - italy - japan - korea - malaysia - malta - mexico - morocco - the neth erlands - singapore - spain - sweden - switzerland - taiwan - thailand - united kingdom - u.s.a. http://www.st.com TDA7449 17/17

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